IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
5.2 Unilink Programming Registers
The Unilink Programming Registers are used to synchronize and supervise all Unilink port and speed-
expansion bus logic. For information about using these registers, see Section 6.2 Speed-Expansion Bus
Initialization on page 155 and Section 6.3 Port Initialization and Operation on page 159.
Unilink port logic contains 32 Unilink receivers and 32 Unilink transmitters. Each of the eight Unilink receive
macros includes four Unilink receivers and one internal phase-locked loop (PLL), and each of the eight
Unilink transmit macros includes four Unilink transmitters and one internal PLL.
Unilink speed-expansion bus logic contains 16 Unilink receivers and 16 Unilink transmitters (that is, 8 of each
for the ingress speed-expansion bus and 8 of each for the egress speed-expansion bus).
Note: In the register notation that follows:
• UL TxPort = Unilink port transmitter
• UL RxPort = Unilink port receiver
• UL TxSpex Bus = Unilink speed-expansion bus transmitter
• UL RxSpex Bus = Unilink speed-expansion bus receiver
5.2.1 UL Global Register
This register is used to specify the Unilink global port and speed-expansion bus settings.
Address
x‘09’
Access Type
Reset Value
Read/Write
‘0000 0000 0000 0000 0000 0000 0000 0000’
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Register Descriptions
Page 72 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
