IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
5.1.3 Unilink PLL Programming Register
Address
x‘03’
Access Type
Reset Value
Read/Write
‘1000 0000 0000 0000 0000 0000 0000 0000’
Reserved
Range A
Range B
Multiplier
Tune
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Description
Bit(s)
0
Field Name
PLL Reset
When set to ‘1’, holds the PLL in a reset state. Should not be released until the reference clock is
stable and the PLL is programmed correctly.
1:8
Reserved
Range A (2:0)
Reserved
Reserved.
9:11
Used to select the PLL output frequency. Must be set to ‘111’.
Reserved.
12
13:15
16:19
20:21
22:31
Range B (2:0)
Multiplier (3:0)
Reserved
Not used. Must be set to ‘111’.
Defines the PLL feedback divider. Must be set to ‘0101’.
Reserved.
Tune (9:0)
Used to optimize PLL stability and jitter. Must be set to ‘01 1011 1110’.
5.1.4 Unilink PLL Status Register
Address
x‘04’
Access Type
Reset Value
Read Only
‘u000 0000 0uuu uuuu uuuu uuuu uuuu uuuu’, where ‘u’ = undefined
Reserved
Observe Bits
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Description
Bit(s)
0
Field Name
PLL Locked
Reserved
When set to ‘1’, the feedback clock is in phase with the reference clock.
1:8
Reserved.
9:31
Observe Bits
Used for testing (23 bits [22:0]).
Register Descriptions
Page 68 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
