IBM PowerPRS Q-64G
Preliminary
Packet Routing Switch
Bit(s)
Field Name
Description
RxPorts Unilink Macro
Enable
0
1
2
3
When set to ‘0’, keeps the Unilink port receive macros in a reset state.
TxPorts Unilink Macro
Enable
When set to ‘0’, keeps the Unilink port transmit macros in a reset state.
RxSpex Bus Unilink
Macro Enable
When set to ‘0’, keeps the Unilink speed-expansion bus receive macros in a reset state.
When set to ‘0’, keeps the Unilink speed-expansion bus transmit macros in a reset state.
TxSpex Bus Unilink
Macro Enable
Hardware Auto Disable
on Port Signal Lost
Enable
When set to ‘1’, enables the Unilink port attachment logic to reset the line when a signal is lost (used
for testing). Must be set to ‘0’.
4
5
6
7
Hardware Auto Disable
on Port Sync Lost
Enable
When set to ‘1’, enables the Unilink port attachment logic to reset the line when synchronization is
lost (used for testing). Must be set to ‘0’.
Hardware Auto Disable
on Spex Bus Signal
Lost Enable
When set to ‘1’, enables the Unilink speed-expansion bus attachment logic to reset the line when a
signal is lost (used for testing). Must be set to ‘0’.
Hardware Auto Disable
on Spex Bus Sync Lost
Enable
When set to ‘1’, enables the Unilink speed-expansion bus attachment logic to reset the line when
synchronization is lost (used for testing). Must be set to ‘0’.
8
9
Port High Speed
Port Half Rate
Reserved for testing. Must be set to ‘0’.
When set to ‘1’, the Unilink macro runs at half the nominal speed (used for testing). Must be set
to ‘0’.
Selects the Unilink port receive macro coupling type:
0
1
AC coupling
DC coupling
10
Port AC/DC
Must be set to ‘1’.
11
12
Spex High Speed
Spex Half Rate
Reserved for testing. Must be set to ‘0’.
When set to ‘1’, the Unilink macro runs at half the nominal speed (used for testing). Must be set
to ‘0’.
Selects the Unilink speed-expansion bus receive macro coupling type:
0
1
AC coupling
DC coupling
13
Spex AC/DC
Reserved
Must be set to ‘1’.
14:15
16:19
Reserved.
RxPorts Elastic Buffer Defines the offset between the Unilink clock deskew memory device read and write pointers. Must
Offset be set to 8.
TxPorts Elastic Buffer Defines the offset between the Unilink clock deskew memory device read and write pointers. Must
Offset be set to 8.
20:23
24:27
28:31
RxSpex Elastic Buffer Defines the offset between the Unilink clock deskew memory device read and write pointers. Must
Offset be set to x‘C’.
TxSpex Elastic Buffer Defines the offset between the Unilink clock deskew memory device read and write pointers. Must
Offset be set to 4.
prsq-64g.01.fm
December 20, 2001
Register Descriptions
Page 73 of 199
IBM [ IBM ]
