IBM3229P2035
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IBM Packet Routing Switch Serial Interface Converter
3.10.2 Processor Interface Lines
Figure 22: IBM Packet Routing Switch Serial Interface Converter Processor Interface Lines
MP_DATA[7:0]
MP_DATA_PRTY
MP_ADD[7:0]
MP_ADD_PRTY
MP_WR
MP_PRDY
MP_SEL
MP_INT
MP_CLK
MP_PRTY_ENB
MP_BURST_MODE
3.10.3 Processor Interface I/O Lines Description
The processor interface is synchronized to the external processor clock. This clock operates at a different
frequency than the switch fabric clock.
Pin Name
I/O
Width
8 bits
Description
bidirectional Data Bus - Hi-Z when no access being processed.
MP_DATA_[7:0]
BiDi
MSB
7
LSB
0
Data Byte ODD Parity Bit - Hi-Z when no access being processed. The converter
checks during write operation and generates during read operation. Parity checker
can be disabled.
MP_DATA_PRTY
BiDI
1 bit
Address Bus
MP_ADD[7:0]
MP_ADD_PRTY
MP_WR
In
In
In
8 bits
1 bit
1 bit
MSB
7
LSB
0
Address Bus ODD Parity - converter checks during read and write access. Default
is parity checker disabled.
Read/Write line
Low
High
Read Operation Write Operation
Ready signal - Asserted High when data is valid on the bus (for read) or when data
is written into converter (for write). Driven by converter. Hi-Z when converter not
selected
MP_PRDY
Out
MP_SEL
MP_CLK
MP_INT
In
In
IBM Packet Routing Switch Serial Interface Converter Selected when LOW
Processor Interface clock Fmax 66 MHz
Out
Converter Processor Interrupt. Asserted low when interruption is pending
prssi.02.fm
March 1, 2001
Functional Description
Page 51 of 154
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