IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
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3.9 IBM Packet Routing Switch Serial Interface Converter RESET Scheme
Description
The converter allows total and selective reset. PATHX and PATHY can be reset together or independently.
The ingress and egress interfaces and their associated FIFOs are reset independently. External reset,
programmable reset, and power-on-reset are implemented in the converter.
3.9.1 Reset Strategy
The converter is reset when power-on-reset (POR) is active. T/S drivers are in Hi-Z state and bidirectional I/
Os are sourced to receiver mode. The µp_interface and configuration table register are reset, and then the
PE interface, FIFOs and their associated logic, and PATH_X/Y are reset.
When RESET_X is active, PATH_X is reset. When RESET_Y is active, PATH_Y is reset. DASL _X/Y differ-
ential drivers are in Hi-Z state.
The µP_interface initiates the reset by a write access to the bit that needs to be reset. A second write access
is necessary to restore the bit to its inactive position.
The following table shows the different reset cases:
Table 13: Register Reset Settings
Module
Configuration Table Registers
POR
X
@A0 bit 0
@A0 bit 1
via BIT Configuration
MP_INTERFACE
X
PE_PLL
X
@9C bit 15
@A0 bit 8
@A0 bit 8
@08 bit 10
@28 bit 10
@A0 bit 8
@90 bit 15
@08 bit 11
@28 bit 11
@A0 bit 4
@A0 bit 5
@94 bit 15
@A0 bit 2
@A0 bit 3
UTOPIA-3 PE Interface
LU_FRAMING
X
X
PATH_X INGRESS FIFO
PATH_Y INGRESS FIFO
WORD_UNFRAMING
SWITCH_X_PLL
X
X
X
X
X
X
PATH_X EGRESS FIFO
PATH_Y EGRESS FIFO
RESET PATH_X_SDC
RESET PATH_Y_SDC
SWITCH_Y_PLL
X
X
X
X
X
X
X
X
X
RESET X_DASL
X
X
X
RESET Y_DASL
X
3.9.2 Power-On-Reset (POR) Procedure
The POR action uses the external MP_CLK microprocessor clock to reset the chip. All drivers are set to high
impedance during the POR. The register table controlling those output lines must be reconfigured after POR.
Functional Description
Page 48 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
