IBM3229P2035
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IBM Packet Routing Switch Serial Interface Converter
Table 12: External Clocks Description
Clock Name
Speed
Description
Differential input receiver clock lines. The associated PLL (SWITCH_X_PLL) delivers
both 200 - 250 MHz (DASL_X250_CLK) and 100 - 125 MHz (DASL_X125_CLK) to
clock the DASL_X and the path X glue logic. An additional input is provided to connect
an external oscillator TEST_CLCK or the MP_CLK instead of the SWITCH_X_CLK on
the PLL_X input.
SWITCH_X_CLK +/-
50 - 62.5 MHz
SWX_TC_source_enb_l[1:0] is located in the configuration table registers (@A0 bits 25
- 24).
Differential input receiver clock lines. The associated PLL (SWITCH_Y_PLL) delivers
both 200 - 250 MHz (DASL_Y250_CLK) and 100 - 125 MHz (DASL_Y125_CLK) to
clock the DASL_Y and the path Y glue logic. An additional input is provided to connect
an external oscillator TEST_CLK or the MP_CLK instead of the SWITCH_Y_CLK on the
PLL_Y input.
SWITCH_Y_CLK +/-
50 - 62.5 MHz
SWY_TC_source_enb_l[1:0] is located in the configuration table registers (@A0 bits 15
- 14).
Single-ended receiver clock line. This is the transfer/synchronization clock issued from
the PE to synchronize transfers on RXDATA[31:0]. It is connected to the PE_PLL which
delivers the URXCLK /UTXCLK for the ingress/egress interfaces. The PE_CLK input is
controlled by PLL_PE_RESET (@9C bit 15) and is turned in BYPASS mode in case
PLL_PE_RESET = ’1’. Programming PLL_PE_RESET at ’1’ disables the PE_PLL from
delivering the necessary clocks for the ingress/egress interfaces.
PE_CLK
MP_CLK
50 and 125 MHz
30 - 66 MHz
Single-ended receiver clock line. This is a free running clock which must be available at
POR when the MP_CLK directly clocks the configuration table registers to provide cor-
rect register map initialization.
Protocol engine clocks. They are single-ended output driver clock lines that allow the
transfer and synchronization of the RXDATA[31:0] and the TXDATA[31:0] to and from
the converter. They are derived from clock sources selected through the setting of regis-
ter @A0, bits 21, 22, and 26 (To_smooth_PLL_In) and bits 30-31 (UCLK_Source_1).
PE_RXCLK_out/
PE_TXCLK_out
Single-ended receiver clock line. It is applied to the ingress interface by programming
the RXDATA_KEEPER register @C0 bit 2 at '1'. When the RXDATA_KEEPER is equal
to '0', Shadow_RxClk_Out is routed to the ingress PE interface (this setting is used for
switch loopback application).
Shadow_RXCLK_in
Shadow_RxClk_Out
50 and 125 MHz
A single-ended output driver clock line derived directly (not going through any clock tree)
from PE PLL output. It connects to the Shadow_RxClk_In through either the PE chip or
the board (via a delay) to provide the best sampling point of the received data from the
protocol engine.
3.8.1 IBM Packet Routing Switch Serial Interface Converter Internal Clocks Description
The converter clock tree is articulated around three PLLs and the microprocessor (MP_CLK) clock. Seven
clock domains exist to clock the converter. The clock generator acts as a programmable selector. UTXCLK
and URXCLK internal clock trees are generated from several clock sources that are selected by programming
the "UCLK_source_l [1:0]" and "XY_SW_source_enb_l [1:0]" in the configuration table registers.
3.8.2 IBM Packet Routing Switch Serial Interface Converter External Traffic:
External traffic from the converter and the IBM 28.4 G Packet Routing Switch (switch) is timed using the two
edges of the clock issued from the SWITCH_X_PLL or the SWITCH_Y_PLL. SWITCH_X/Y_PLLs deliver two
clocks which are 100 - 125 MHz (DASL_X125_CLK) and 200 - 250 MHz (DASL_X250_CLK) respectively.
The X/Y transmit and the X/Y receive DASLs are clocked by DASL_X250_CLK and DASL_Y250_CLK
respectively. Receive and transmit data is then input and output at a frequency of 400 - 500 MHz. At each
occurrence of the DASL_X/Y250_CLK clock edge, transition data is sent to or received from the switch.
prssi.02.fm
Functional Description
Page 47 of 154
March 1, 2001
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