IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
3.9.4 PLL Reset
Once a reset is established, the software must reconfigure the SWITCH_PLL X/Y bit or PLL_PE bit 15 to ‘0’
(system mode).
Table 16: System Mode PLL Resets
Reset Name
Impact
Reset
Exclusive - No impact on
other PLLs
SWITCH_X_PLL
Program @90 SWITCH_PLL_X bit 15 at ‘1’ in the configuration table registers.
Exclusive - No impact on
other PLLs
SWITCH_Y_PLL
PLL_PE
Program @94 SWITCH_PLL_Y bit 15 at ‘1’ in the configuration table registers.
Program @9C PLL_PE bit 15 at ‘1’ in the configuration table registers.
Exclusive - No impact on
other PLLs
3.9.5 Ingress/Egress Interface Reset
Ingress and egress interfaces are reset on software request. An interface reset restores the internal sched-
uler to the idle phase. Transfer data is lost and internal registers are swapped to their reset position. Signals
that drive the PE outputs are switched so to hold the PE interface drivers in inactive state.
Both ingress and egress PE interfaces are reset simultaneously by programming @A0 CONFIG_reg bit 8 at
‘1’ in the configuration table registers. Once the reset is established, the software must reconfigure the @A0
CONFIG_reg bit 8 at ‘0’ (system mode).
3.10 Microprocessor Interface Description
The IBM Packet Routing Switch Serial Interface Converter (the converter) chip is initialized and controlled via
a processor interface which works on an 8-bit data bus and operates in two modes. The external input pin
MP_BURST_SEL selects the operational mode (low - 8-bits mode and high - 32-bits mode):
• 8-bit mode (byte mode): The converter registers are considered single 8-bits registers and are addressed
via MP_ADD[7:0] address bus signals. Each register access is a single-beat access of one byte.
• 32-bit mode (burst mode): The converter registers are considered as single 32-bits registers and are
addressed via MP_ADD[7:2] address bus signals. Each access is a burst access of four bytes. The burst
order is the following: data bits [7:0], data bits [15:8], data bits [23:16], and data bits [31:24].
3.10.1 The microprocessor interface:
• Provides read/write access to all chip registers
• Provides DASL picocode downloading
• Provides error reporting
• Collects the converter interrupts and pass them to the attached processor.
• Monitors all interrupt signals generated by other converter functional blocks and, when one is asserted,
latches and holds the value until the interrupt event register is read and reset.
• Provides the necessary handshake protocol to interface the attached processor, including address bus
decoding, wait state insertion, data bus drivers control, and optional parity checking on both the data and
address busses.
Functional Description
Page 50 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
