IBM3229P2035
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IBM Packet Routing Switch Serial Interface Converter
After POR action, the converter must be re-configured via the µP_interface. The PLLs are switched into
BYPASS mode and neither PATH X nor PATH Y are configured.
POR external signal is an asynchronous signal. POR initiates when the POR signal input is going down. POR
procedure stops when the POR signal input is held up. POR must be asserted for at least 10 MP_CLK cycles
to insure proper chip reset.
The following table shows pin/pad TEST I/O initialization values (the values during and after reset):
Table 14: I/O Initialization Values
Pin Name
CE1_A
CE1_B
CE1_C1
CE1_C2
CE0_IO
CEO_Scan
CE0_TEST
TEST_B2
TEST_C3
DI1
Value in System
Description
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
LSSD test A clock
LSSD test B clock
LSSD test C clock
LSSD test C clock
Used to force the JTAG EXTEST operation
A and B clock gating, used also to Clock Splitter GATE input
Used to control Boundary Scan feature
LSSD test B clock (if required)
LSSD test C clock (if required)
Driver Inhibit (for non test I/O)
Driver Inhibit (for test I/O)
DI2
RI
Receiver Inhibit
TDI
JTAG serial input
TCK
JTAG clock
TMS
JTAG control signal
TRST
JTAG asynchronous reset
3.9.3 Path Reset
Individual PATH X and PATH Y resets are performed by addressing an appropriated bit in the
COMMON_CONFIG_REGISTER @A0 (CCR). SWITCH_X_PLL or SWITCH_Y_PLL must run during the
PATH X/Y reset action. PLLs are not affected by PATH X/Y resets, but the PLL must be reset when an
external loopback is initiated with a new clock source (PLL needs a delay to lock). Once a reset is estab-
lished, the software must reconfigure the CCR @A0 bits 0, 1, 2, 3 into the system mode.
Table 15: Path Resets
Reset Name
PATH X
Impact
Reset
No impact on PATH Y
no impact on PATH X
no impact on DASL_Y
no impact on DASL_X
Program CCR @A0 bit 0 at ‘1’ in the configuration table registers.
Program CCR @A0 bit 1 at ‘1’ in the configuration table registers.
Program CCR @A0 bit 2 at ‘1’ in the configuration table registers.
Program CCR @A0 bit 3 at ‘1’ in the configuration table registers.
PATH Y
DASL_X
DASL_Y
prssi.02.fm
March 1, 2001
Functional Description
Page 49 of 154
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