IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
3.8 Clocks Generator Description
Figure 21: Clocks Distribution Diagram
LU Serializer
CRC Insert
Synch/Idle/Yellow
Packet Generator
Receive
Interface_X
3 Cell FIFOs
LU Framing
Header Insertion
Parity Checking
Idle Discard
RX_INT
Ingress
Interface
Bus
Keeper
LU Serializer
CRC Insert
Receive
Synch/Idle/Yellow
Packet Generator
Interface_Y
3 Cell FIFOs
Shadow_RXCLK_in
50 Mhz ....62.5 MHz
URXCLK
Shadow_RXCLK_out
SWITCH_X_CLK
+
11
10
01
00
200 MHz ... 250 MHz
SWITCH_X_PLL
SWITCH_X_CLK
-
100 MHz ... 125 MHz
SWX_TC_source_enb_l[1:0]
SWY TC_source_enb_l[1:0]
A0-bit 21,22,26
µp interface
Configuration
Table
tied 1.
Registers
Test_Clk
MP_CLK
UCLK_source_l[1:0]
11
10
01
tied 0.
MP_CLK
PE_CLK
(30 MHz ..66 MHz)
(50 MHz ..125 MHz)
TO_SMOOTH_PLL_in
00
(30 MHz ..66 MHz)
External
Smoothing
PLL
11
00
PLL_PE
01
10
tied 1.
FROM_SMOOTH_PLL_out
00
SWITCH_Y_PLL
01
10
11
PLL_PE_RESET @9C bit 15
100 MHz ... 125 MHz
SWITCH_Y_CLK
SWITCH_Y_CLK
+
200 MHz ... 250 MHz
PE_RXCLK_out
PE_TXCLK_out
-
LU Deserializer
CRC Check
Header Extraction
Header Checking
50 Mhz ....62.5 MHz
UTXCLK
Transmit DASL
Interface_X
6 Cell FIFOs
6 Cell FIFOs
Mux
TX_INT
Egress
Word Framing
Header insertion
Parity Generation
Idle Insertion
LU Deserializer
CRC Check
Header Extraction
Header Checking
Transmit DASL
Interface_Y
Interface
SWITCH_X_INSERVICE
SWITCH_Y_INSERVICE
Table 11: Selecting the Signal That Appears on the TO_SMOOTH_PLL_IN Signal
SelectX_Y
@A0-22
Forcepath
@A0-21
SW_X_IN
SW_Y_IN
Smooth_select _enable_I@A0-26
To_Smooth_ PLL_In
X
X
0
0
1
1
X
X
X
0
1
0
1
X
0
1
1
1
0
0
0
0
X
1
1
1
1
1
1
0
SWITCH_X
SWITCH_Y
MP_CLK
SWITCH_Y
SWITCH_X
MP_CLK
0
X
X
X
X
X
Functional Description
Page 46 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
