IBM3009K2672
IBM SONET/SDH Framer
PHY Layer Interface Pin Descriptions (Sheet 3 of 4)
Pin Name
Pin No.
I/O
Type
Pin Description
RXUDATA(15)
RXUDATA(14)
RXUDATA(13)
RXUDATA(12)
RXUDATA(11)
RXUDATA(10)
RXUDATA(9)
RXUDATA(8)
RXUDATA(7)
RXUDATA(6)
RXUDATA(5)
RXUDATA(4)
RXUDATA(3)
RXUDATA(2)
RXUDATA(1)
RXUDATA(0)
AC06
AB06
AD07
AB07
Y07
AE08
AD08
AB08
Y08
Receive Data Out: Tri-stateable 16-bit cell data output bus, enabled only
in cycles following those with RXENB asserted low. Bit 0 is the LSB.
UTOPIA Level 1: RXUDATA(15:8) is the data byte output for receive
UTOPIA Level 1 interface 1. Bit 15 is the MSB and is the first bit
received. RXUDATA(7:0) is the data byte output for receive UTOPIA
Level 1 interface 2. Bit 7 is the MSB and is the first bit received.
UTOPIA Level 2: RXUDATA(15:0) is the word output for the receive
UTOPIA Level 2 interface. Bit 15 is the most significant bit and is the
first bit received.
UTOPIA Level 2+: RXUDATA(15:0) is the word input for the receive
UTOPIA Level 2+ interface. Bit 15 is the most significant bit and is the
first bit received.
O (T)
LVTTL-5fp
V08
AD09
AB09
Y09
W09
V09
Y10
Receive Physical Device Address:
UTOPIA Level 1: RXUADDR(2) is the receive Enable input, for
receive UTOPIA Level 1 interface 2.
RXUADDR(4)
RXUADDR(3)
RXUADDR(2)
RXUADDR(1)
RXUADDR(0)
AE10
AC10
AB10
AB11
AD11
UTOPIA Level 2: Five-bit wide address for the ports programmed in
this device is provided on RXUADDR(4:0). Bit 0 is the LSB. If single-
PHY operation is performed, such as when STM-4c or STS-12c
frames are processed, then these pins should be set to ’0’.
UTOPIA Level 2+: Five-bit wide address for the ports programmed in
this device is provided on RXUADDR(4:0). Bit 0 is the LSB. If single-
PHY operation is performed, such as when STM-4c or STS-12c
frames are processed, then these pins should be set to ’0’.
I
LVTTL-5sp
LVTTL-5fd
Receive Parity Output: (Active high)
Parity bit for UTOPIA Level 2+, Level 2, and Level 1 #1 interfaces. Parity
can be generated over data, or over data and control signals, depending
on a control bit setting. Parity can also be selected to be odd or even.
RXPRTY
V10
O (T)
Receive Start of Cell/Chunk Output: (Active high)
Tri-stateable output, enabled only in cycles following those with RXENB
asserted low. RXSOC indicates the start of each chunk or ATM cell for
UTOPIA Level 2+, Level 2, and Level 1 #1 interfaces.
RXSOC
RXSOFO
RXENB
AD12
U09
O (T)
O (T)
I
LVTTL-5fd
LVTTL-5fd
LVTTL-5sp
Receive Start-of-Frame Output: (Active high)
Used only during UTOPIA Level 2+ operation, this pin indicates the start of
a new block of frame data.
Receive Read Enable Input: (Active low)
Read enable input signal for UTOPIA Level 2+, Level 2, and Level 1 #1
interfaces. Data and control outputs, except for the RXCLAV(3:0) signals,
are output on the clock cycle following the assertion of this signal low.
AE06
Pin Information
Page 34 of 279
ssframer.01
8/27/99
IBM [ IBM ]
