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IBM3009K2672 参数 Datasheet PDF下载

IBM3009K2672图片预览
型号: IBM3009K2672
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, CBGA474, CERAMIC, BGA-474]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 287 页 / 4239 K
品牌: IBM [ IBM ]
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IBM3009K2672  
IBM SONET/SDH Framer  
Clock Monitor Status and Mask Registers  
The clock monitor status register bits indicate the loss of a specific island’s clock. They are set whenever a  
difference between the clock test signal and the individual island’s clock acknowledge signal occurs after the  
clock monitor test period. ClkStat1 consists of pointer bits that indicate active clock status errors in  
ClkStat2/3/4.  
For each bit position: 0: Normal operation of the corresponding clock island  
1: The corresponding island clock is lost  
An active bit of these registers is reset by restoring the clock of the corresponding clock island and by writing  
a ‘1’ into the corresponding bit position. Reading one register will reset all bits of this register if the “clear-reg-  
ister” option is set in bit ConfGP1(3).  
The clock monitor mask registers ClkMask2/3/4 control the propagation of active clock monitor status signals  
to bits 7/6/5 of ClkStat1. ClkMask1 controls propagation to the signal FElocCS (bit 1 of IRQGP1 register). The  
mask registers allow read and write access.  
For each bit position: 0: The corresponding clock status bit is masked (DEFAULT)  
1: The corresponding clock status bit is active (for ClkMask1, the corresponding bit  
activates the signal FElocCS (bit 1 of IRQGP1 register))  
4.1: ClkStat1, ClkMask1 [3830 H Status, 3838 H Mask]  
Signal Name  
Reserved  
ClkStat4  
Bits  
4:0  
5
Access  
R/W  
Default  
Description  
00000  
Reserved (pointers)  
R/W  
0
0
0
Pending active clock status error indication in ClkStat4 register  
Pending active clock status error indication in ClkStat3 register  
Pending active clock status error indication in ClkStat2 register  
ClkStat3  
6
R/W  
ClkStat2  
7
R/W  
4.2: ClkStat2, ClkMask2 [3831 H Status, 3839 H Mask]  
Signal Name  
Bits  
Access  
Default  
Description  
PH_Tx4  
PH_Tx3  
PH_Tx2  
PH_Tx1  
ACI_Rx2  
ACI_Rx1  
ACI_Tx2  
ACI_Tx1  
0
1
2
3
4
5
6
7
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0
0
0
0
0
0
0
0
Clock island PH_Tx4 lost clock  
Clock island PH_Tx3 lost clock  
Clock island PH_Tx2 lost clock  
Clock island PH_Tx1 lost clock  
Clock island ACI_Rx2 lost clock  
Clock island ACI_Rx1 lost clock  
Clock island ACI_Tx2 lost clock  
Clock island ACI_Tx1 lost clock  
Register Descriptions  
Page 124 of 279  
ssframer.01  
8/27/99  
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