IBM3009K2672
IBM SONET/SDH Framer
Watchdog Timer Period Register
WDTGP1: Divider ratio to derive the interface time-out period from the GPPCLK clock. This register is reset
to FF H whenever a timeout occurs; it has to be reconfigured by a GPP write access. The purpose of the
watchdog timer is to set a limit as to how long an access is allowed to last before that access is terminated by
the GPDTACK/GPRDY signal being forced active. A maskable interrupt can be generated to the external
microprocessor when the watchdog timer times out.
The watchdog timer counts the number of GPPCLK clocks since the time that a register has been accessed.
The access will terminate when either of the following two events occurs:
1. The watchdog timer times out (the GPDTACK/GPRDY signal is forced active so that the cycle termi-
nates). In this case the write does not occur or the read does not return valid data.
2. The cycle terminates naturally.
6.1: WDTGP1 [3849 H]
Signal Name
Bits
7:0
Access
R/W
Default
Description
WDTGP1(7:0)
11111111 Number of GPPCLK clock cycles per time-out period
ssframer.01
8/27/99
Register Descriptions
Page 127 of 279
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