IBM3009K2672
IBM SONET/SDH Framer
Clock Monitor Test Period Register
CMonGP1: Divider ratio to derive the clock monitor test period from the GPPCLK clock. Clock monitoring is
disabled if equal to 00 H (DEFAULT). A 50 MHz GPPCLK frequency results in a maximum of 5.1 µs for the
clock test period. This allows clock islands down to a frequency of 197 kHz to be monitored.
Note: If the UTOPIA interface clocks go below 197 kHz when a 50 MHz GPPCLK clock is used and the
Clock Monitor Test Period Register is set to FF H, then an interrupt will be generated because the UTOPIA
clock period will be smaller than the clock monitor test period. In this case, the interrupt could be masked or
the Clock Monitor Test Period Register can be set to 00 H.
5.1: CMonGP1 [3848 H]
Signal Name
Bits
7:0
Access
R/W
Default
Description
CMonGP1(7:0)
00000000 Number of GPPCLK cycles/test period
Register Descriptions
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ssframer.01
8/27/99
IBM [ IBM ]
