IBM3009K2672
IBM SONET/SDH Framer
Handshaking Error Indication and Mask Registers
The local handshaking error indication registers indicate pending handshaking error requests from the
GPPINT chiplet. HShake1 consists of pointer bits that indicate active requests in registers HShake2/3/4/5.
For each bit position: 0: Normal operation of the corresponding chiplet
1: The corresponding chiplet did not de-assert its DTACK signal
Exception: The signals TOError and IntError (HShake5(1:0)) have the following meaning:
3.1: TOError and IntError Meanings
TOError
0
IntError
0
Description
Normal operation
GPP de-asserts strobes without waiting for GPDTACK assertion. This means that the external microproces-
sor, instead of inserting more wait states, has de-asserted either GPSEL or GPDS (GPRD/GPWR in Intel
mode) before the GPDTACK signal was asserted.
0
1
Watchdog Timeout in REST state. A timeout in this state indicates that the chiplet addressed in the current
read cycle has a problem.
1
1
0
1
Watchdog Timeout in REQ state. A timeout in this state indicates that the SONET/SDH framer was busy work-
ing on the prior read or write transaction when the timeout occurred and the current transaction has also failed.
An active bit of the handshaking error indication registers is reset by removing the cause for the malfunction-
ing of the chiplet and by writing a ‘1’ into the corresponding bit position. Reading one of these registers will
reset all bits of this register if the “clear-register” option is set in ConfGP1(2).
The handshaking error indication mask register bits control the propagation of the GPPINT handshaking error
requests to bits 7 to 4 of register HShake1. HSMask1 controls propagation to the signal FElocHS (bit 0 of
IRQGP1 register). The mask registers allow read and write access.
For each bit position: 0: The corresponding handshaking error indication bit is masked (DEFAULT)
1: The corresponding request bit is active (for HSMask1, the corresponding request bit
activates signal FElocHS (bit 0 of IRQGP1 register))
3.2: HShake1, HSMask1 [3820 H Error, 3828 H Mask]
Signal Name
Bits
Access
Default
Description
Reserved
HShake5
HShake4
HShake3
HShake2
0:3
4
R/W
R/W
R/W
R/W
R/W
0000
Reserved (pointers)
0
0
0
0
Pending HS error active in HShake5
Pending HS error active in HShake4
Pending HS error active in HShake3
Pending HS error active in HShake2
5
6
7
ssframer.01
8/27/99
Register Descriptions
Page 121 of 279
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