Data Sheet
Preliminary
PowerPC 970FX
Table 3-23. Mode Select Type Input Signals
Pin
Description
Bus configuration
Comment
Pin
AA19, AC19, AB16
AA14
BUS_CFG(0:2)
CKTERM_DIS
PLL_MULT
Select processor clock to bus clock ratio
Disable internal clock receiver terminator
Clock receiver termination
Select between multiplier 8 or 12
PLL range select
AA8
PLL_RANGE(1:0)
PROCID(0:2)
AA9, AB7
Processor ID
For multi processor environment
L19, M19, M18
Table 3-24. Debug Pins
Pin
AVP_RESET
EI_DISABLE
GPULDBG
Description
Comment
Pin
W23
P20
For manufacturing test only
Turns off elasticity in the processor interface.
2
970FX debug
Pull up to OV for debug mode, JTAG - I C interaction
AA22
DD
Electrical and Thermal Characteristics
Page 35 of 74
October 14, 2005
IBM [ IBM ]
