Data Sheet
Preliminary
PowerPC 970FX
Figure 3-11 provides the test access port timing diagram.
Figure 3-11. Test Access Port Timing Diagram
TCK
5
4
TDI, TMS
Input Data (Valid)
6
Output Data (Valid)
TDO
7
TDO
TDO
Output Data (Invalid)
8
3.10.3 I2C and JTAG Considerations
For systems using only JTAG, TDO should be pulled up (tied to OVDD), and the I2C data and clock pins
should also be tied to OVDD. For systems using only I2C, TCK, TMS, TDO, and TDI should be pulled down. If
the system needs to support both JTAG and I2C access, pulldown resistors must be implemented on the
JTAG pins. These resistors maintain the proper state on the JTAG pins when I2C access is active. These
pulldown resistors must be able to be overridden for JTAG operation. Additionally, the JTAG driver hardware
connected to the 970FX should drive its outputs low (on TCK, TMS, TDI) when JTAG is idle. Systems using
multiple PowerPC 970FXs in multiprocessor configurations should not daisy chain JTAG scan chains if I2C is
supported. They should connect the JTAG scan chains in parallel (TCK, TDI, etc., tied together) and use
separate TMS inputs to select each 970 processor for JTAG access.
Note: TRST should always be pulled up to OVDD on the PowerPC 970FX.
3.10.4 Boundary Scan Considerations
The PowerPC 970FX does not support the BSDL standard for implementing boundary scan testing. The IBM
technical library contains an application note titled PowerPC 970FX Boundary Scan, which describes a
method of producing the equivalent function.
Electrical and Thermal Characteristics
October 14, 2005
Page 39 of 74
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