Data Sheet
Preliminary
PowerPC 970FX
Figure 3-7. Asynchronous Input Timing
2
ALL ACTIVE
LOW INPUTS
VM
VM
3
1
3
2
1
VM
VM
ALL ACTIVE
HIGH INPUTS
Notes:
1. No reference to SYSCLK because these inputs are sampled using the internal processor clock.
2. Define maximum rise/fall time as <1ns.
3. Define minimal pulse length >10ns.
4. VM = Midpoint Voltage (OV /2)
DD
5. These timings refer to the following pins: INT, MCP, QACK, HRESET ,SRESET, TBEN, THERM_INT, and TRIGGERIN.
6. The legend for this figure is provided by callout number inTable 3-16.
3.6.1 TBEN Input Pin
The TBEN input pin can be used as either an enable for the internal timebase/decrementer or as an external
clock input. The mode is controlled by the setting of HID0 bit 19. When this bit is 0, the timebase and
decrementer update at 1/8th the processor core frequency whenever TBEN is high (traditional enable mode).
When HID0 bit 19 is 1, the timebase and decrementer are clocked by the rising edge of TBEN (external clock
input mode). When the external clock input mode is used the TBEN input frequency must not exceed 1/16th
of the core processor’s maximum frequency.
Electrical and Thermal Characteristics
October 14, 2005
Page 31 of 74
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