Data Sheet
Preliminary
PowerPC 970FX
3.8 Mode Select Input Timing Specifications
This section provides timing specifications for the mode-select pins. These pins are sampled by HRESET.
Table 3-22 provides the input AC timing specifications as defined in Figure 3-8 on page 34 . The mode-select
signals and debug pins are listed in Table 3-23 on page 35 and Table 3-24 on page 35.
Table 3-22. Input AC Timing Specifications
Value
Call Out
Number
Characteristic
Unit
Notes
Minimum
>1
Maximum
1
HRESET Width
BYPASS Width
—
—
—
—
—
—
ms
—
—
2
200
20
µs
3
Mode select signal setup
Mode select inputs hold time
PLL control signal setup
PLL control inputs hold time
Processor clocks
Processor clocks
Processor clocks
Processor clocks
1, 5
1
4
1000
20
5
6
2,3
2,3
20
Notes:
1. Mode select pins must not change level sooner than 20 processor clocks before the falling edge of HRESET and must
be held for a minimum of 1000 processor clocks after the rising edge of HRESET.
2. PLL control pins must not change level earlier than 20 processor clocks before the rising edge of BYPASS and must
be held for a minimum of 20 processor clocks after the rising edge of HRESET.
3. PLL control inputs must not change while HRESET is low.
4. For a timing diagram, see Figure 3-8 on page 34 and Figure 3-9 on page 36 .
5. Guaranteed by design and not tested.
Electrical and Thermal Characteristics
October 14, 2005
Page 33 of 74
IBM [ IBM ]
