Data Sheet
PowerPC 970FX
Preliminary
Table 3-25. JTAG AC Timing Specifications (Dependent on SYSCLK)
CallOut
Number
Characteristic
TCK cycle time
Minimum
Maximum
Unit
Notes
1
32
15
0
—
—
2
Processor clocks
2, 5
2, 5
3, 5
5
2
TCK clock pulse width
Processor clocks
3
TCK rise and fall times
ns
ns
ns
ns
ns
ns
4
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
0
—
—
12
9
5
15
2.5
3
5
6
4, 5
3, 5
5
7
8
TCK to TDO high impedance
TCK to output data invalid (output hold)
0
—
Notes:
1. TCK frequency is limited by the core processor frequency.
2. Processor clock cycles.
3. Guaranteed by characterization and not tested.
4. Minimum specification guaranteed by characterization and not tested.
5. JTAG timings are dependent on an active SYSCLK.
6. For a timing diagram, see Figure 3-10 on page 38 and Figure 3-11 on page 39 .
Figure 3-10. JTAG Clock Input Timing Diagram
1
2
2
TCK
VM
VM
VM
3
3
VM = Midpoint Voltage (0V /2)
DD
Note: The legend for this figure is provided in Table 3-25.(Dependent on SysClk)
Electrical and Thermal Characteristics
Page 38 of 74
October 14, 2005
IBM [ IBM ]
