Data Sheet
Preliminary
PowerPC 970FX
2
3.10 I C and JTAG
3.10.1 I2C Bus Timing Information
The I2C bus specification can be downloaded from Philips Semiconductors web site at
http://semiconductors.philips.com.
The PowerPC 970FX I2C bus is limited to a speed of 50KHz for the standard-mode timing specification and
does not support the high-speed (Hs-mode) or fast-mode timing.
The PowerPC 970FX I2C pins are limited to OVDD voltages. Level shifting and/or pullups may be required to
interface to higher voltage devices. See the Philips I2C bus specifications for recommendations on level
shifting and pullups.
Note: To avoid problems in determining the proper pullup resistor value, it is recommended that level-
shifted 970FX I2C bus pins not be wired together with non-970FX parts in a system. Each 970FX should
have its own private level shifter.
3.10.2 IEEE 1149.1 AC Timing Specifications
Table 3-25 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 3-10 on page 38
and Figure 3-11 on page 39 . The five JTAG signals are as follows:
1. TDI
2. TDO
3. TMS
4. TCK
5. TRST
Note: The following are some of the PowerPC 970FX’s non-standard IEEE AC timing implementations:
1. Refer to Section 3.9.3 I2C and JTAG Considerations to determine pullups/pulldowns for configuration of
TCK, TDI, and TMS
2. Systems using multiple PowerPC 970FXs in multiprocessor configurations should not daisy chain JTAG
scan chains if I2C is supported. They should connect the JTAG scan chains in parallel (TCK, TDI, etc.,
tied together) and use separate TMS inputs to select each 970 processor forJTAG access.
3. JTAG operations need the core clock to be operating usually with PLL in bypass. CLKIN and CLKIN must
receive at least 16 pulses for TCK down level and 16 pulses for TCK up level.
Table 3-25. JTAG AC Timing Specifications (Dependent on SYSCLK)
CallOut
Number
Characteristic
Minimum
TBD
Maximum
1/16
Unit
Notes
1, 5
—
TCK frequency of operation
Core processor frequency
Notes:
1. TCK frequency is limited by the core processor frequency.
2. Processor clock cycles.
3. Guaranteed by characterization and not tested.
4. Minimum specification guaranteed by characterization and not tested.
5. JTAG timings are dependent on an active SYSCLK.
6. For a timing diagram, see Figure 3-10 on page 38 and Figure 3-11 on page 39 .
Electrical and Thermal Characteristics
Page 37 of 74
October 14, 2005
IBM [ IBM ]
