Data Sheet
PowerPC 970FX
Preliminary
Figure 3-8. HRESET and BYPASS Timing Diagram
All power supply voltages stable and
SYSCLK ramp up completed
Power
>100ns before INITCORE
1
SRESET
500µs
100µs
>1ms
HRESET
200µs
800µs
2
BYPASS
800µs
PLL stable
PLL_LOCKED
4
3
Mode Select Inputs 1
5
6
PLL Control Inputs2
Reference
Time A
Notes:
1. These timings refer to the following pins: BUS_CFG(0:2), PROCID(0:2).
2. These timings refer to the following pins: CKTERM_DIS, PLL_MULT, and PLL_RANGE(1:0).
These pins may only be changed by driving HRESETand BYBASS low.
3. HRESET and BYPASS may be low during initial IPL stages and not have to transition power prior to reference time A
4. PLL control inputs must not change while HRESET is low.
5. The legend for this figure is provided by callout number in Table 3-22 on page 33.
Electrical and Thermal Characteristics
October 14, 2005
Page 34 of 74
IBM [ IBM ]
