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IBM25PPC604E3DB--250E 参数 Datasheet PDF下载

IBM25PPC604E3DB--250E图片预览
型号: IBM25PPC604E3DB--250E
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 250MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255]
分类和应用: 时钟外围集成电路
文件页数/大小: 29 页 / 525 K
品牌: IBM [ IBM ]
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1.7.0.1 Mechanical Dimensions of the CBGA Package
CBGA package.
2X
0.2
A1 CORNER
D
A
C
0.15 C
E
E1
2X
0.2
B
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Millimeters
DIM
A
A1
A2
b
D
D1
e
E
E1
MIN
MAX
2.50
3.30
0.79
0.99
1.00
1.40
0.82
0.93
21.00 BSC
5.00
16.00
1.27 BSC
21.00 BSC
5.00
16.00
e/2
A2
A1
A
e
255X
e/2
b
0.3 C A B
0.15 C
Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application
of the 604e.
1.8.1 PLL Configuration
The 604e PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency,
the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL
configuration for the 604e is shown in Table 11 for nominal frequencies.
20
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM