Table 10. Pinout Listing for the CBGA Package (Continued)
Signal Name
WT
VDD
VOLTDETGND
2
XATS
D02
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06,
J08, J09, J11, K07, K10, L06, L08, L09, L11
F03
J16
Low
I/O
Pin Number
Active
Low
—
I/O
Output
—
Notes:
1. These are test signals for factory use only and must be pulled up to Vdd for normal machine operation.
2. NC (no-connect) in the 604; internally tied to GND in the 604e CBGA package to indicate to the power
supply that a low-voltage processor is present.
3. To operate in accordance with these specifications, the drive mode signals must be configured with
DRVMOD0 = high, and DRVMOD1 = high.
1.7 Package Description
The package parameters for the 604e are provided in the following list. The package type is 21 mm, 256-
lead ceramic ball grid array (CBGA).
Package outline
Interconnects
Pitch
Maximum module height
Ball diameter
21 x 21 mm
255
1.27 mm (50 mil)
3.30 mm
0.89 mm (35 mil)
9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
19