Table 11. PLL Configuration
PLL_CFG
[0–3]
CPU Frequency in MHz
(VCO Frequency in MHz)
CPU/
SYSCLK
Ratio
VCO
Multiplier
Bus
25
MHz
Bus
33.3
MHz
Bus
40
Bus
50
Bus
60
Bus
66.6
MHz
Bus
83.3
MHz
Bus
100
MHz
Bin
Dec
MHz
MHz
MHz
0000
0001
0
1
1:1
1:1
x2
x8
—
—
—
—
—
—
—
—
—
—
—
40
50
60
66
83.3
(320) (400) (480)
(533)
(666)
1100
0100
12
4
1.5:1
2:1
x2
x2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
(400)
0110
1000
1110
1010
0111
1011
1001
1101
0101
0010
6
8
2.5:1
3:1
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
208
(416)
250
(500)
200
(400)
250
(500)
300
(600)
14
10
7
3.5:1
4:1
—
—
210
(420)
233
(466)
292
(584)
350
(700)
—
200
(400) (480)
240
266
(532)
333
(666)
—
—
—
—
—
—
—
4.5:1
5:1
—
225 270
300
(600)
—
—
—
—
—
—
(450) (540)
250 300
11
9
200
333
(666)
(400) (500) (600)
5.5:1
6:1
220 275 330
(440) (550) (660)
—
—
—
—
13
5
200
(400)
240
(480) (600)
300
—
—
—
6.5:1
7:1
216
(433)
260
(520) (650)
325
2
233
280 350
(466)
(560) (700)
PLL bypass
Clock off
0011
1111
3
15
Notes:
1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see
Section 1.4.2.2, “Input AC Specifications,” for valid SYSCLK and VCO frequencies.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is
disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
9/17/99 Revision 1.4
PID9q-604e Hardware Datasheet
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IBM [ IBM ]
