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IBM25PPC604E3DB--250E 参数 Datasheet PDF下载

IBM25PPC604E3DB--250E图片预览
型号: IBM25PPC604E3DB--250E
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 250MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255]
分类和应用: 时钟外围集成电路
文件页数/大小: 29 页 / 525 K
品牌: IBM [ IBM ]
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1.8.2 Input and Output Signal Mode Selection  
The PID9q-604e’s input buffers can be configured through the connection of the ARRAY_WR  
signal to provide input hysteresis and enable the CLKOUT signal. If the ARRAY_WR signal is  
connected to OVdd, the PID9q-604e will select the Hysteresis Off input buffer threshold mode, and  
the CLKOUT signal is enabled, which is the default mode for this specification. When Hysteresis  
OFF mode is selected the VM is 0.9V.  
If ARRAY_WR is connected to GND, Hysteresis On mode is selected, and the CLKOUT signal is  
placed in a high impedance state. When Hysteresis On mode is selected, the VM is 1.3V, and the  
input transition points are 1.1V for V and 1.5V for V . Hysteresis On mode provides for greater  
IL  
IH  
noise immunity on inputs, and the input hold time requirement for Low to High transitions is  
increased.  
When the ARRAY_WR signal is connected to the HRESET signal, Hysteresis On mode is  
selected, and the CLKOUT signal is enabled. If the ARRAY_WR signal is connected to an inverted  
HRESET signal, Hysteresis Off mode is selected, and the CLKOUT signal is placed in a high  
impedance state.  
Table 12 below shows the configuration of the ARRAY_WR signal to select input signal hysteresis  
and enable the CLKOUT signal.  
Table 12. Input Signal Hysteresis and CLKOUT Signal Configuration  
Signal  
ARRAY_WR  
Connected to  
Mode Selected  
Notes  
OVdd  
GND  
Hyteresis Off  
CLKOUT Enabled  
1
Hyteresis On  
CLKOUT high impedance  
HRESET signal  
HRESET  
Hyteresis On  
CLKOUT Enabled  
Hyteresis Off  
2
CLKOUT high impedance  
Notes:  
1. Default Mode  
2.HRESET is the inverted state of the HRESET signal  
The PID9q-604e implements a Fast Out output mode which allows increased system bus  
frequencies. The PID9q-604e can be configured for Fast Out mode by connecting the  
L2_TSTCLK signal to GND or the HRESET signal. When Fast Out mode is enabled, the output  
valid and output hold times are reduced. If the L2_TSTCLK signal is connected to OVdd or to an  
inverted HRESET, compatibility mode is selected.  
22  
PID9q-604e Hardware Datasheet  
IBM  
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE