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IBM25PPC604E3DB--250E 参数 Datasheet PDF下载

IBM25PPC604E3DB--250E图片预览
型号: IBM25PPC604E3DB--250E
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 250MHz, CMOS, CBGA255, 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255]
分类和应用: 时钟外围集成电路
文件页数/大小: 29 页 / 525 K
品牌: IBM [ IBM ]
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Table 13 describes the configuration of the L2_TSTCLK signal to select Fast Out or compatibility  
output modes.  
Table 13. FastOut/Compatibility Output Signal Configuration  
Signal  
L2_TSTCLK  
Connected to  
Mode Selected  
Compatibility  
Notes  
OVdd  
GND  
FastOut  
1
2
HRESET  
HRESET  
FastOut  
Compatibility  
Notes:  
1. Default Mode  
2.HRESET is the inverse state of the HRESET signal  
1.8.3 PLL Power Supply Filtering  
The AVdd power signal is provided on the 604e to provide power to the clock generation phase-  
locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal  
should be filtered using a circuit similar to the one shown in Figure 11. The circuit should be placed  
as close as possible to the AVdd pin to ensure it filters out as much noise as possible.  
10 Ω  
Vdd  
(1.8 V Nom.)  
AVdd  
10 µF  
0.1 µF  
GND  
Figure 11. PLL Power Supply Filter Circuit  
1.8.4 Decoupling Recommendations  
Due to the 604e’s large address and data buses, and high operating frequencies, the 604e can  
generate transient power surges and high frequency noise in its power supply, especially while  
driving large capacitive loads. This noise must be prevented from reaching other components in  
the 604e system, and the 604e itself requires a clean, tightly regulated source of power. Therefore,  
it is strongly recommended that the system designer place at least one decoupling capacitor with  
a low ESR (effective series resistance) rating at each Vdd and OVdd pin of the 604e.  
These capacitors should range in value from 220 pF to 10 mF to provide both high- and low-  
frequency filtering, and should be placed as close as possible to their associated Vdd pin. Surface-  
mount tantalum or ceramic devices are preferred. It is also recommended that these decoupling  
capacitors receive their power from Vdd and GND power planes in the PCB, utilizing short traces  
to minimize inductance in the traces. Power and ground connections must be made to all external  
Vdd and GND pins of the 604e.  
1.8.5 Connection Recommendations  
To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal  
9/17/99 Revision 1.4  
PID9q-604e Hardware Datasheet  
23  
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE