PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 6 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Interrupts Interface
5V tolerant
IRQ00:10
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
I
I
1, 5
3.3V LVTTL
IRQ11:12
3.3V PCI
JTAG Interface
3.3V CMOS
w/pull-up
TCK
Test Clock.
I
1
4
3.3V CMOS
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V CMOS
w/pull-up
1
5
3.3V CMOS
w/pull-up
TRST
Test Reset.
I
System Interface
SysClk
5V tolerant
Main system clock input.
Clock
O
3.3V LVTTL
5V tolerant
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this
bidirectional pin low (minimum of 16 cycles) to initiate a
system reset. A system reset can also be initiated by
software. Implemented as an open-drain output (two
states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
5V tolerant
TmrClk
Halt
Processor timer external input clock.
Halt from external debugger.
I
3.3V LVTTL
5V tolerant
3.3V LVTTL
I
1, 4
General purpose I/O 0 through 10. To access these
functions, software must set DCR register bits.
5V tolerant
GPIO00:31
TestEn
I/O
3.3V LVTTL
1.8V CMOS
w/pull-down
Test Enable.
I
I
I
I
3
5V tolerant
3.3V LVTTL
RcvrInh
RefVEn
DrvrInh1:2
Receiver Inhibit. Active only when TestEn is active.
Reference Voltage Enable. Used for wafer testing. Do
not connect for normal operation.
1.8V CMOS
w/pull-down
Driver Inhibit. Used for test purposes only. Tie up for
normal operation
5V tolerant
3.3V LVTTL
2
Page 47 of 72
5/13/04
IBM [ IBM ]
