PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 7 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
5V tolerant
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
3.3V LVTTL
Trace data capture clock, runs at 1/4 the frequency of
the processor.
5V tolerant
3.3V LVTTL
Trace Execution Status is presented every fourth
processor clock cycle.
5V tolerant
TrcES0:4
TrcTS0:6
I/O
I/O
3.3V LVTTL
Additional information on trace execution and branch
status.
5V tolerant
3.3V LVTTL
Power Pins
AGND
PLL (analog) voltage ground.
Ground.
n/a
n/a
n/a
n/a
GND
1.8V—Filtered voltages input for PLLs (analog circuits)
Note: A separate filter for each of the three voltages is
recommended.
AxVDD
n/a
n/a
OVDD
3.3V supply—I/O (except DDR SDRAM)
2.5V supply—DDR SDRAM
n/a
n/a
n/a
n/a
n/a
n/a
SVDD
VDD
1.8V supply—Logic voltage.
Reserved Pins
Do not connect signals, voltage, or ground to these
balls.
Reserved
n/a
n/a
Page 48 of 72
5/13/04
IBM [ IBM ]
