PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
UART Peripheral Interface
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory. This input can be individually connected to
either or both UART0 and UART1.
5V tolerant
3.3V LVTTL
UARTSerClk
I
1, 4
5V tolerant
UART0_Rx
UART0 Receive data.
I
O
I
1, 4
4
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART0_Tx
UART0 Transmit data.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Receive data.
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
6
5V tolerant
3.3V LVTTL
I
6
5V tolerant
3.3V LVTTL
I
1, 4
4
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
4
5V tolerant
3.3V LVTTL
1, 4
1, 4
1, 4
1, 4
1, 4
5V tolerant
3.3V LVTTL
UART1_Rx
I/O
I/O
I/O
I/O
5V tolerant
3.3V LVTTL
UART1_Tx
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_DSR/CTS
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_RTS/DTR
IIC Peripheral Interface
IIC0SClk
5V tolerant
3.3V LVTTL
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
1, 2
1, 2
1, 2
1, 2
5V tolerant
3.3V LVTTL
IIC0SDA
IIC1SClk
IIC1SDA
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Page 46 of 72
5/13/04
IBM [ IBM ]
