PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
PCIXReset
Description
I/O
Type
Notes
Brings PCI device registers and logic to a consistent
state.
O
3.3V PCI
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
PCIXSErr
I/O
3.3V PCI
4
Indicates the current target is requesting the master to
stop the current transaction.
PCIXStop
I/O
I/O
3.3V PCI
3.3V PCI
4
4
Indicates the target agent’s ability to complete the
current data phase of the transaction.
PCIXTRDY
DDR SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
BankSel0:3
CAS
ClkEn0:3
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
DM0:8
O
2.5V SSTL_2
2.5V SSTL_2
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane.
DQS0:8
I/O
ECC0:7
ECC check bits 0:7.
Memory address bus.
I/O
O
2.5V SSTL_2
2.5V SSTL_2
MemAddr00:12
MemClkOut0
MemClkOut0
Subsystem clock.
O
I/O
I
2.5V SSTL_2
2.5V SSTL_2
MemData00:63
MemVRef1:2
Memory data bus.
Voltage Ref
Receiver
Memory reference voltage (SVREF) input.
RAS
Row Address Strobe.
Write Enable.
O
O
2.5V SSTL_2
2.5V SSTL_2
WE
Ethernet Interface
EMCCD,
MII: Collision detection
RMII 1: Receive error
5V tolerant
I/O
I/O
O
EMC1RxErr
3.3V LVTTL
EMCCrS,
EMC0CrSDV
MII: Carrier sense
RMII 0: Carrier sense data valid
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
EMCMDClk
EMCMDIO
MII and RMII: Management data clock
MII and RMII: Transfer command and status information
between MII and PHY
5V tolerant
3.3V LVTTL
I/O
Page 43 of 72
5/13/04
IBM [ IBM ]
