PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
EMCRxD0:3,
Description
I/O
Type
Notes
MII: Receive data
EMC0RxD0:1,
EMC1RxD0:1,
EMC0RxD,
RMII 0: Receive data
RMII 1: Receive data
SMII 0: Receive data
SMII 1: Receive data
5V tolerant
3.3V LVTTL
I/O
EMC1RxD
EMCRxDV,
MII: Receive data valid
5V tolerant
I
I
I
I
EMC1CrSDV
RMII 1: Carrier sense data valid
3.3V LVTTL
5V tolerant
3.3V LVTTL
EMCRxClk
MII: Receive clock
EMCRxErr,
EMC0RxErr
MII: Receive error
RMII 0: Receive error
5V tolerant
3.3V LVTTL
EMCTxClk,
EMCRefClk
MII: Transmit clock
RMII and SMII: Reference clock
5V tolerant
3.3V LVTTL
5
EMCTxD0:3,
EMC0TxD0:1,
EMC1TxD0:1,
EMC0TxD,
MII: Transmit data
RMII 0: Transmit data
RMII 1: Transmit data
SMII 0: Transmit data
SMII 1: Transmit data
5V tolerant
3.3V LVTTL
O
EMC1TxD
EMCTxEn,
EMC0TxEn,
EMCSync
MII: Transmit data enabled
RMII 0: Transmit data enabled
SMII: Sync signal
5V tolerant
O
O
3.3V LVTTL
EMCTxErr,
EMC1TxEn
MII: Transmit error:
RMII: Transmit data enabled
5V tolerant
3.3V LVTTL
External Slave Peripheral Interface
Used by the PPC440GP to indicate that data transfers
5V tolerant
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
O
I
have occurred.
3.3V LVTTL
Used by slave peripherals to indicate they are prepared
to transfer data.
5V tolerant
3.3V LVTTL
1, 5
1, 5
5V tolerant
3.3V LVTTL
End Of Transfer/Terminal Count.
I/O
Peripheral address bus used by PPC440GP when not in
external master mode, otherwise used by external
master.
Note: PerAddr00 is the most significant bit (msb) on this
bus.
5V tolerant
3.3V LVTTL
PerAddr00:31
I/O
1
5V tolerant
PerWBE0:3
PerBLast
External peripheral data bus byte enables.
I/O
I/O
O
1, 2
1, 4
2
3.3V LVTTL
Used by either the peripheral controller, DMA controller,
or external master to indicates the last transfer of a
memory access.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
PerCS0:7
External peripheral device select.
Page 44 of 72
5/13/04
IBM [ IBM ]
