PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description (Part 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Peripheral data bus used by PPC440GP when not in
external master mode, otherwise used by external
master.
Note: PerData00 is the most significant bit (msb) on this
bus.
5V tolerant
3.3V LVTTL
PerData00:31
I/O
1
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GP is the bus master, it enables the selected
DDR SDRAMs to drive the bus.
5V tolerant
PerOE
O
2
1
3.3V LVTTL
5V tolerant
3.3V LVTTL
PerPar0:3
PerReady
External peripheral data bus byte parity.
I/O
I
Used by a peripheral slave to indicate it is ready to
transfer data.
5V tolerant
3.3V LVTTL
Used by the PPC440GP when not in external master
mode, as output by either the peripheral controller or
DMA controller depending upon the type of transfer
involved. High indicates a read from memory, low
indicates a write to memory.
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
5V tolerant
PerR/W
PerWE
I/O
1, 2
2
3.3V LVTTL
Write Enable. Low when any of the four PerWBE0:3
signals are low.
5V tolerant
3.3V LVTTL
O
O
External Master Peripheral Interface
Bus Request. Used when the PPC440GP needs to
regain control of peripheral interface from an external
master.
5V tolerant
3.3V LVTTL
BusReq
External Acknowledgement. Used by the PPC440GP to
indicate that a data transfer occurred.
5V tolerant
ExtAck
ExtReq
ExtReset
HoldAck
HoldReq
PerClk
O
I
3.3V LVTTL
External Request. Used by an external master to
indicate it is prepared to transfer data.
5V tolerant
3.3V LVTTL
1, 4
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
O
I
Hold Acknowledge. Used by the PPC440GP to transfer
ownership of peripheral bus to an external master.
5V tolerant
3.3V LVTTL
Hold Request. Used by an external master to request
ownership of the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
1, 5
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
I/O
External Error. Used as an input to record external
master errors and external slave peripheral errors.
5V tolerant
3.3V LVTTL
PerErr
Page 45 of 72
5/13/04
IBM [ IBM ]
