PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—All speeds (Part 2 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for
33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
Internal Peripheral Interface
IICSCL
na
na
n
na
na
a
na
na
na
19
19
12
12
IICSDA
na
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
n
n
n
a
a
a
12
12
12
8
8
8
n
a
n
a
12
8
n
a
n
n
a
12
8
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
UART1_Rx
UART1_Tx
UARTSerClk
a
n
a
a
12
8
8
na
na
12
12
8
8
na
n
na
a
n
12
n
a
n
a
n
a
n
a
na
na
na
12
na
na
8
na
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
12
8
JTAG Interface
TCK
TDI
na
na
12
na
na
na
na
8
async
async
async
async
async
TDO
TMS
TRST
na
na
Page 52 of 60
6/20/03
IBM [ IBM ]
