PowerPC 405GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings (Continued)
Parameter
Min
Max
Units
ns
TmrClk input high time
TmrClk input low time
Note:
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded
Processor User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T
is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for
OPB
266MHz parts.
Input Setup and Hold Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Output Delay and Float Timing Waveform
Clock
T
max
min
T
max
min
T
OV
max
min
OV
OV
T
T
T
Outputs
OH
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
Page 50 of 60
6/20/03
IBM [ IBM ]
