PowerPC 405GP Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is
read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest
SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or
pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to
+3.3V or 10kΩ to +5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions
only during reset. They are used for other signals during normal operation. The following table lists the
strapping pins along with their functions and strapping options. The pin for the 456-ball package is listed first
(for example, AF3), followed by the corresponding pin for the 413-ball package (for example, U8), which
appears as AF3/U8. The signal names assigned to the pins for normal operation follow the pin numbers.
PPC405GP Strapping Pin Assignments (Part 1 of 2)
Function
Option
Ball Strapping
AF2/T8
1
AF3/U8
AD16/AB15
UART0_DTR UART0_RTS
PLL Tuning
UART0_Tx
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 111011
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 111101
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 111110
Choice 8; TUNE[5:0] = 100100
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
D16/A17
DMAAck0
B15/B14
DMAAck1
PLL Forward Divider
Bypass mode
Divide by 3
Divide by 4
Divide by 6
0
0
1
1
0
1
0
1
2
B14/A15
DMAAck2
C12/A8
DMAAck3
PLL Feedback Divider
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
P25/R23
EMCTxD3
L24/J22
EMCTxD2
PLB Divider from CPU
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
L25/K21
EMCTxD1
J26/F22
EMCTxD0
OPB Divider from PLB
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
Page 56 of 60
6/20/03
IBM [ IBM ]
