PowerPC 405GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405GP. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the PPC405GP the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405GP with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405GP peripherals impose more stringent requirements (see
Note 1).
• Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock
tracks the modulation.
• Use the SDRAM MemClkOut since it also tracks the modulation.
Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for
additional details. This application note is available on the IBM Microelectronics web site at
http://www.chips.ibm.com.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates. If an external serial clock is used the baud rate is
unaffected by the modulation.
2. Operation of the PPC405GP PCI Bridge is unaffected by the use of a SSCG.
For PCI frequencies of 33.33 MHz and below the PCI controller supports synchronous mode operation.
This is accomplished by strapping the PPC405GP for synchronous mode PCI and connecting the PCI bus
clock to the PPC405GP SysClk input. For 33.33 MHz signalling, the PCI specification has no limitation on
the amount of frequency deviation or modulation that may be applied to the PCI clock. Therefore, the
PPC405GP SSCG requirements stated above take precedence.
At PCI frequencies above 33.33 MHz, the PCI controller must be operated in asynchronous mode. When
in asynchronous mode, the PCI bus clock must be driven into the PPC405GP PCIClk input. In this
configuration the PCI controller supports the 66.66 MHz PCI clock specification which specifies a
maximum frequency deviation of -1% at a modulation of between 30 kHz and 33 kHz.
3. Ethernet operation is unaffected.
4. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405GP meets the above
requirements and does not adversely affect other aspects of the system.
Page 48 of 60
6/20/03
IBM [ IBM ]
