PowerPC 405GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
Min
Note 1
15
Max
66.66
Note 1
33.33
40
Units
MHz
ns
25
MHz
ns
30
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
PCIClk input low time
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
–
MHz
ns
400
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
160
–
ns
160
–
ns
2.5
25
400
–
MHz
ns
PHYTxClk period
40
PHYTxClk input high time
35% of nominal period
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
PHYRxClk period
2.5
25
400
–
MHz
ns
40
PHYRxClk input high time
35% of nominal period
ns
PHYRxClk input low time
35% of nominal period
–
ns
PerClk output frequency–133MHz
PerClk period–133MHz
–
30
–
33.33
–
MHz
ns
PerClk output frequency–200MHz
PerClk period–200MHz
50
–
MHz
ns
20
–
PerClk output frequency–266MHz
PerClk period–266MHz
66.66
–
MHz
ns
15
PerClk output high time
45% of nominal period 55% of nominal period
45% of nominal period 55% of nominal period
± 0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
ns
1000/(2T
+2ns)
OPB
–
MHz
UARTSerClk input frequency (Note 3)
UARTSerClk period
2T
T
+2
–
n
n
s
s
s
OPB
+1
UARTSerClk input high time
–
OPB
T
+1
UARTSerClk input low time
TmrClk input frequency–133MHz
TmrClk period–133MHz
–
33.33
–
n
OPB
–
MHz
ns
30
–
TmrClk input frequency–200MHz
TmrClk period–200MHz
50
MHz
ns
20
–
–
TmrClk input frequency–266MHz
TmrClk period–266MHz
66.66
–
MHz
ns
15
Page 49 of 60
6/20/03
IBM [ IBM ]
