PowerPC 405GP Embedded Processor Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing values of na means “not applicable” and dc
means “don’t care.”
2. See “Test Conditions” on page 46 for output capacitive loading.
I/O Specifications—All speeds (Part 1 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for
33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI Interface
PCIAD31:0
PCIC3:0[BE3:0]
PCIClk
3
3
0
0
6
6
1
1
0.5
0.5
na
1.5
1.5
na
PCI Clock
PCI Clock
1
1
async
1
dc
3
dc
0
na
6
na
1
PCIDevSel
PCIFrame
0.5
0.5
1.5
1.5
PCI Clock
PCI Clock
3
0
6
1
1
PCIGnt0[Req]
PCIGnt1:5
na
na
6
1
0.5
1.5
PCI Clock
1
PCIIDSel
3
na
3
0
na
0
6
dc
6
1
dc
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
1
PCIINT[PerWE]
PCIIRDY
async
1
1
1
PCIParity
PCIPErr
3
0
6
1
3
0
6
1
PCIReq0[Gnt]
PCIReq1:5
5
0
na
na
na
na
PCI Clock
1
PCIReset
na
na
3
na
na
0
na
na
6
na
na
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCISErr
PCIStop
1
1
PCITRDY
3
0
6
1
Ethernet Interface
EMCMDClk
na
na
0
settable
2
9
9
6
6
2, async
2
1 OPB clock 1 OPB clock
period + 10ns
EMCMDIO[PHYMDIO]
100
EMCMDClk
period
EMCTxD3:0
EMCTxEn
EMCTxErr
PHYCol
na
na
na
na
na
na
20
20
20
2
2
2
9
9
6
6
PHYTX
PHYTX
PHYTX
2
2
9
6
2
9
6
2, async
2, async
2, async
2
PHYCrS
9
6
PHYRxClk
PHYRxD3:0
PHYRxDV
PHYRxErr
PHYTxClk
na
9
na
6
4
4
4
1
1
1
na
na
na
na
na
na
PHYRX
PHYRX
PHYRX
9
6
2
9
6
2
na
na
2, async
Page 51 of 60
6/20/03
IBM [ IBM ]
