PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications—All speeds (Part 3 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for
33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
System Interface
DrvrIn
h1:2
dc
dc
n
a
n
a
n
a
n
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
12
na
8
Halt
dc
dc
dc
na
dc
n
na
n
na
async
RcvrIn
SysClk
SysErr
SysReset
TestEn
TmrClk
h
a
n
a
n
a
n
a
n
a
n
a
n
na
10
na
na
na
1
12
12
na
na
8
8
async
asyn
c
dc
dc
dc
dc
na
na
na
na
async
async
Page 53 of 60
6/20/03
IBM [ IBM ]
