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IBM25PPC405GP-3EE266CZ 参数 Datasheet PDF下载

IBM25PPC405GP-3EE266CZ图片预览
型号: IBM25PPC405GP-3EE266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 266.66MHz, CMOS, PBGA413, 25 X 25 MM, ENHANCED, PLASTIC, BGA-413]
分类和应用: 时钟外围集成电路
文件页数/大小: 60 页 / 1410 K
品牌: IBM [ IBM ]
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PowerPC 405GP Embedded Processor Data Sheet  
I/O Specifications—266MHz  
Notes:  
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the  
command is used by SDRAM.  
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.  
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the  
PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes  
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal  
wiring.  
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.  
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.  
Input (ns)  
Output (ns)  
Output Current (mA)  
I/O H I/O L  
(maximum) (minimum)  
Signal  
Clock  
Notes  
Setup Time Hold Time Valid Delay  
Hold Time  
(T min)  
(T min)  
(T max)  
(T min)  
IS  
IH  
OV  
OH  
SDRAM Interface  
BA1:0  
na  
na  
na  
na  
na  
na  
1.5  
na  
1.5  
na  
na  
na  
na  
na  
na  
na  
na  
1
5.7  
4.8  
5.7  
4.2  
4.8  
4.8  
4.8  
5.7  
4.9  
5.7  
5.7  
1
1
1
1
1
1
1
1
1
1
1
19  
19  
19  
40  
19  
19  
19  
19  
19  
19  
19  
12  
12  
12  
25  
12  
12  
12  
12  
12  
12  
12  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
MemClkOut  
1, 2  
2
BankSel3:0  
CAS  
1, 2  
2
ClkEn0:1  
DQM0:3  
2
DQMCB  
2
ECC0:7  
2
MemAddr12:0  
MemData0:31  
RAS  
na  
1
1, 2  
2
na  
na  
1, 2  
1, 2  
WE  
External Slave Peripheral Interface  
DMAAck0:3  
DMAReq0:3  
EOT0:3/TC0:3  
PerAddr0:31  
PerBLast  
na  
4
na  
1
6
na  
6
0
na  
0
12  
na  
12  
19  
12  
8
na  
8
PerClk  
PerClk  
PerClk  
PerClk  
PerClk  
dc  
3
dc  
1
7.2  
6
0
12  
8
3
1
0
PerCS0  
PerCS1:7[GPIO10:16]  
n
a
n
a
6
6
0
0
12  
8
8
PerClk  
PerClk  
PerData0:31  
PerOE  
5
n
1
a
1
1
1
1
7.2  
n
0
a
19  
12  
PerClk  
12  
PerPar0:3  
PerR/W  
3
7.2  
6
0
19  
12  
na  
12  
12  
8
PerClk  
PerClk  
PerClk  
PerClk  
4
0
PerReady  
PerWBE0:3  
6.5  
3
na  
6
na  
0
na  
8
External Master Peripheral Interface  
BusReq  
ExtAck  
ExtReq  
ExtReset  
HoldAck  
HoldPri  
HoldReq  
PerClk  
n
n
a
a
n
a
6
6
0
0
12  
8
8
PerClk  
PerClk  
n
a
12  
4
1
n
a
n
a
n
a
n
na  
na  
3
na  
na  
1
6
0
19  
12  
na  
na  
19  
na  
12  
8
PerClk  
PerClk  
PerClk  
PerClk  
PLB Clk  
PerClk  
6
0
na  
na  
0.9  
na  
na  
na  
0.7  
na  
na  
na  
12  
na  
4
1
na  
3
na  
1
4
PerErr  
Page 55 of 60  
6/20/03  
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