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IBM25EMPPC750DBUB2660 参数 Datasheet PDF下载

IBM25EMPPC750DBUB2660图片预览
型号: IBM25EMPPC750DBUB2660
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 44 页 / 514 K
品牌: IBM [ IBM ]
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abled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.  
Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.  
4. In Clock - off mode, no clocking occurs inside the PPC740 or PPC750 regardless of the SYSCLK input.  
5. This limit is 83.3MHz as specified in Section 3.1.2.1, “Clock AC Specifications“.  
Table 17 provides sam ple core-to-L2 frequ en cies.  
1
Table 17. Sample Core-to-L2 Frequencies  
Core  
Frequency  
in MHz  
÷1  
÷1.5  
÷2  
÷2.5  
÷3  
200  
225  
233  
250  
266  
133.3  
100  
80  
112.5  
116.5  
125  
90  
93.2  
100  
83.3  
88.6  
133  
106.4  
Note:  
1. Although the PPC750 is designed for L2 bus ratios of 1:1, 1.5:1, 2:1, 2.5:1 and 3:1, this specification  
supports the L2 frequency range specified in Section 3.1.2.4, “L2 Clock AC Specifications“. For higher  
L2 frequencies not supported in this document, please contact your IBM marketing representative.  
8.2 PLL Power Supply Filtering  
Th e AVdd an d L2AVdd power sign als are provided on th e PPC740 an d PPC750 to pro-  
vide power to th e clock gen eration ph ase-locked loop an d L2 cach e delay-locked loop  
respectively. To en su re stability of th e in tern al clock, th e power su pplied to th e AVdd  
in pu t sign al sh ou ld be filtered u sin g a circu it sim ilar to th e on e sh own in Figu re 17 .  
Th e circu it sh ou ld be placed as close as possible to th e AVdd pin to en su re it filters ou t  
as m u ch n oise as possible. An iden tical bu t separate circu it sh ou ld be placed as close  
as possible to th e L2AVdd pin .  
10 Ω  
V
AV (or L2AVdd)  
DD  
DD  
10 µF  
0.1 µF  
GND  
Figure 17. PLL Power Supply Filter Circuit  
8.3 Decoupling Recommendations  
Du e to th e PPC740s an d PPC750s dyn am ic power m an agem en t featu re, large address  
an d data bu ses, an d h igh operatin g frequ en cies, th e PPC740 an d PPC750 can gen erate  
tran sien t power su rges an d h igh frequ en cy n oise in its power su pply, especially wh ile  
drivin g large capacitive loads. Th is n oise m u st be preven ted from reach in g oth er com -  
pon en ts in th e PPC740 an d PPC750 system s, an d th e processor itself requ ires a clean ,  
33 of 44  
PPC740 and PPC750 Hardware Specifications  
Preliminary and subject to change without notice  
 
 
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