8.0 System Design Information
Th is section provides electrical an d th erm al design recom m en dation s for su ccessfu l
application of th e PPC740 an d PPC 750.
8.1 PLL Configuration
Th e PLL for th e PPC740 an d PPC750 is con figu red by th e PLL_CFG[0-3-] sign als. For a
given SYSCLK (bu s) frequ en cy, th e PLL con figu ration sign als set th e in tern al CPU an d
VCO frequ en cy of operation . Th e PLL con figu ration for th e PPC740 an d PPC750 is
sh own in Table 16 for n om in al frequ en cies.
Table 16. PPC740 and PPC750 Microprocessor PLL Configuration
Frequency Range Supported by VCO having an example
Processor
to Bus
range of VCO =300 to VCO
=533 (MHz)
min
max
PLL_CFG
(0:3)
Frequency
Ratio
VCO
Divider
SYSCLK
Core
Min=
Max=
Min=
Max=
VCO
max
bin
dec
(r)
(d)
n/a
2
VCO /(r*d)
VCO
/(r*d)
VCO /d
/d
min
max
min
1
0000
0001
0010
0011
0
1
2
3
Rsv
n/a
n/a
n/a
n/a
2
7.5x
7x
25
35
38
150
266
2
2
25
PLL
Bypass
n/a
n/a
n/a
n/a
n/a
3
1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
5
Rsv
n/a
2
n/a
n/a
41
150
266
2
6.5x
25
1
6
Rsv
n/a
2
n/a
33
50
27
37
30
n/a
59
n/a
150
Off
n/a
266
Off
7
4.5x
3x
5
8
2
83
9
5.5x
4x
2
48
67
53
33
44
10
11
12
13
14
15
2
5x
2
2
8x
2
25
6x
2
25
43
5
3.5x
2
83
4
Off
n/a
n/a
n/a
Notes:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section 3.1.2.1,
“Clock AC Specifications“ for valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is dis-
PPC740 and PPC750 Hardware Specifications
32 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
