8.6 Pull-up Resistor Requirements
Th e PPC740 an d PPC750 requ ire h igh -resistive (weak: 10 KΩ) pu ll-u p resistors on sev-
eral con trol sign als of th e bu s in terface to m ain tain th e con trol sign als in th e n egated
state after th ey h ave been actively n egated an d released by th e PPC740 an d PPC750 or
oth er bu s m asters. Th ese sign als are -- TS, ABB, DBB, an d ARTRY.
In addition , th e PPC750 h as on e open -drain style ou tpu t th at requ ires a pu ll-u p resis-
tor (weak or stron ger: 4.7 KΩ - 1- KΩ) if it is u sed by th e system . Th is sign al is --
CKSTP_OUT.
Du rin g in active periods on th e bu s, th e address an d tran sfer attribu tes on th e bu s are
n ot driven by an y m aster an d m ay float in th e h igh -im pedan ce state for relatively lon g
periods of tim e. Sin ce th e PPC740 an d PPC750 m u st con tin u ally m on itor th ese sign als
for sn oopin g, th is float con dition m ay cau se excessive power draw by th e in pu t receiv-
ers on th e processor or by oth er receivers in th e system . It is recom m en ded th at th ese
sign als be pu lled u p th rou gh weak (10 KΩ) pu ll-u p resistors or restored in som e m an -
n er by th e system , Th e sn ooped address an d tran sfer attribu te in pu ts are -- A[0-31],
AP[0-3], TT[0-4], TBST, an d GBL.
Th e data bu s in pu t receivers are n orm ally tu rn ed off wh en n o read operation is in
progress an d do n ot requ ire pu ll-u p resistors on th e data bu s. Oth er data bu s receivers
in th e system , h owever, m ay requ ire pu ll-u ps, or th at th ose sign als be oth erwise driven
by th e system du rin g in active periods. Th e data bu s sign als are -- DH[0-31], DL[0-31],
an d DP[0-7].
If address or data parity is n ot u sed by th e system , an d th e respective parity ch eckin g
is disabled th rou gh HID0, th e in pu t receivers for th ose pin s are disabled, an d th ose
pin s do n ot requ ire pu ll-u p resistors an d sh ou ld be left u n con n ected by th e system . If
all parity gen eration is disabled th rou gh HID0, th an all parity ch eckin g sh ou ld also be
disabled th rou gh HID0, an d all parity pin s m ay be left u n con n ected by th e system .
No pu ll-u p resistors are n orm ally requ ired for th e L2 in terface.
PPC740 and PPC750 Hardware Specifications
36 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
