Datasheet
Preliminary
CPC945 Bridge and Memory Controller
3.6 Processor Interface Specifications
The CPC945’s dual PowerPC 970xx processor interfaces operate at up to 625 MHz in double-data rate
mode, providing up to 1250 million transfers per second. For the CPC945 to comply with the timing require-
ments of the IBM PowerPC 970MP microprocessor, its internal configuration registers must be initialized at
startup. The settings for these registers must be determined by analysis using the card design electrical char-
acteristics, and optimized experimentally. The open-eye requirement for the CPC945 on the receiving end is
the same as for the IBM PowerPC 970MP microprocessor. The processor link design must be appropriate for
the required bit rate. The operating frequencies for the processor interfaces are generated by the PLL1 from
the PI_APCLK differential signal pair.
The processor interfaces feature an automatic initialization alignment procedure (IAP) that adjusts the timing
skews on all the data lines at the receiving end of the interface. Board wiring flight-time information must be
used to ensure that the maximum data skew figures listed in the IBM PowerPC 970MP RISC Microprocessor
Datasheet are met. Additional requirements for board wiring are contained in that document.
3.7 PCI Express Interface Specification
The PCI Express interface operates at 2.5 GHz and complies with the electrical and timing requirements in
the PCI-SIG, “PCI Express Base Specification Revision 1.0a,” PCI Express, April 15, 2003.
The PCI-SIG, “PCI Express Card Electromechanical Specification Revision 1.0a,” PCI Express, April 15,
2003., should be used to correctly design this interface.
2
3.8 I C Interface Specifications
2
2
The I C slave interface complies with the I C-bus specification for standard-mode operation (100 kbps) and
2
fast-mode operation (400 kbps). The I C master interfaces support standard-mode and operate at selectable
bit rates of 25, 50, and 100 kbps.
2
Table 3-10. I C-Bus Specifications
Standard Mode
Fast Mode
Minimum
Parameter
Symbol
Units
Minimum
Maximum
100
Maximum
400
SCL clock frequency
(slave)
fSCL
fSCL
0
0
0
kHz
kHz
SCL clock frequency
(master)
100
N/A
N/A
Data set-up time
Data hold time
tSU
tHO
tCLH
tCLL
250
02
—
70
—
—
1001
02
—
150
—
ns
ns
μs
μs
SCL clock high time
SCL clock low time
4.0
4.7
0.6
1.3
—
1. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the serial clock (SCL) signal. If such a device
does stretch the low period of the SCL signal, it must send the next data bit to the serial data (SDA) line, tr max + tSU:DAT = 1000 +
250 = 1250 ns (according to the standard-mode I2C-bus specification), before the SCL line is released.
2. A device must internally provide a data hold time to bridge the undefined period between VIH and VIL of the falling edge of the
SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
A15-6009-03
December 18, 2007 - IBM Confidential
Electrical and Thermal Characteristics
Page 29 of 69
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