Datasheet
Preliminary
CPC945 Bridge and Memory Controller
Table 3-7. DDR_REFCLK Reference Clock Specifications
Value
Parameter
Symbol
Unit
Minimum
Maximum
550
Clock rise and fall time
t
RISE tFALL
ps
%
ps
V
Clock duty cycle
45
55
Clock input jitter
tJIT
VICM
VIH
100
DDR_REFCLK common mode voltage level
DDR_REFCLK input high voltage
DDR_REFCLK input low voltage
DDR_REFCLK input voltage range
0
VICM + 0.05
- 0.3
1.8
2.15
V
VIL
VICM + 0.05
V
V
IH - VIL
100
mV
Figure 3-3. PLL Reference Clock Parameters
tCKH
tCKL
tJIT
Reference Clock
tRISE
HT_REFCLK and PCIE_REFCLK PLL inputs can be either LVDS or CMOS. There is no setting required to
select between these two types of input. It is determined strictly by the inputs provided by the system design.
Table 3-8. HT_REFCLK and PCIE_REFCLK Reference Clock Input Specifications for LVDS
Value
Parameter
Symbol
Unit
Notes
1
Minimum
0.35
Maximum
0.55
Clock rise and fall time
t
RISE tFALL
ns
%
Clock duty cycle
45
55
Clock input jitter
tJIT
100
ps
SE peak-to-peak at PLL inputs
V
IH - VIL
250
450
mV
2
Note:
1. LVDS at 20 and 80%.
2. Single ended (SE) means that REFCLK_N and REFCLK_P must each see this swing.
A15-6009-03
December 18, 2007 - IBM Confidential
Electrical and Thermal Characteristics
Page 27 of 69
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