Datasheet
Preliminary
CPC945 Bridge and Memory Controller
3.4.1 Guidelines for PLL Filtering for HyperTransport and PCI Express PLLs (AVDD2, AVDDA, AVDDB)
In general, to control jitter at the card level it is important to ensure that the incoming reference clock signal
has minimal jitter.
• Good system board layout design practices should be followed, especially if the reference clock is derived
from an external crystal.
• On card VDD and GND noise should be minimized through the appropriate use of decoupling capacitors.
The use of a voltage regulator as the source for the analog VDD can also help reduce noise.
• Care should be taken to ensure that the AVDD2 and AVDD pins for the PCI Express and those for the
HyperTransport cores are separately connected to the power plane on the card through individual filter
networks. Connecting multiple AVDD2 or AVDD pins together and feeding them through a common filter
network is not recommended. Modulation between the interface cores might result if a design incorpo-
rates a common filter network.
• Each AVDD2 or AVDD pin should have a filter network (an example of one possible implementation is
shown in Figure 3-1 on page 24). All wire lengths should be kept as short as possible to minimize induc-
tive coupling from other noise sources. The recommended capacitor should be of type X5R ceramic con-
struction, of size 0603, have a 6.3 V rating, and should be located adjacent to the device package. The
impedance of the ferrite bead should be much greater than that of the capacitor for the noise frequencies.
Circuit simulation and experimentation is necessary to determine the optimal filter design.
A15-6009-03
December 18, 2007 - IBM Confidential
Electrical and Thermal Characteristics
Page 25 of 69
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