Datasheet
CPC945 Bridge and Memory Controller
Preliminary
3.4.2 Guidelines for PLL Filtering for Processor Interface and DDR2 (AVDD)
• In general, to control jitter at the system board level it is important to ensure that the incoming reference
clock signal has minimal jitter. Good system board layout design practices should be followed, especially
if the reference clock is derived from an external crystal.
• On card VDD and GND noise should be minimized through the appropriate use of decoupling capacitors.
Use of a voltage regulator as the source of the analog VDD can also help reduce noise.
• Each AVDD pin should have a filter network (an example of one possible implementation is shown in
Figure 3-2 on page 24). All wire lengths should be kept as short as possible to minimize inductive cou-
pling from other noise sources. The recommended capacitor should be of type X5R ceramic construction,
of size 0603, have a 6.3 V rating, and should be located adjacent to the device package. The impedance
of the ferrite bead should be much greater than that of the capacitor for the noise frequencies. Using a
resistor in place of a ferrite bead might be preferable in some applications. Designers should note that
these filter configurations are only recommendations and should only be used as a starting point. Circuit
simulation and experimentation is necessary to determine the optimal filter design.
• The AVDD - AGND compression/expansion due to noise should be less than 50 mV.
3.5 Clocks
Table 3-5. Reference Clock Input Frequencies
Interface
Signal Name
PI_REFCLK
Frequency
Input Type
See the CPC945 User’s Manual,
Tables 12-11 and 12-12
Processor interface
Pseudo HSSTL
DDR
DDR_REFCLK
HT_REFCLK
PCIE_REFCLK
PMR_CLK
66.67 MHz
66.67 MHz
LVDS
CMOS/LVDS
CMOS/LVDS
PECL
HyperTransport
PCI Express
100 MHz
Power management
300 MHz (no PLL)
Table 3-6. PI_REFCLK Reference Clock Specifications
Value
Parameter
Symbol
Unit
Minimum
Maximum
500
Clock rise and fall time
t
RISE, tFALL
ps
%
ps
V
Clock duty cycle
45
55
Clock input jitter
tJIT
VIH
VIL
100
PI_REFCLK input high voltage
PI_REFCLK input low voltage
PI_REFCLK input voltage range
VDD2 + 0.3
- 0.3
0.1
V
V
IH - VIL
V
Electrical and Thermal Characteristics
Page 26 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
IBM [ IBM ]
