Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Figure 3-4. Typical External Termination for LVDS Input
10 nF
10 nF
REFCLKP
REFCLKN
100 ohms
Table 3-9. HT_REFCLK and PCIE_REFCLK Reference Clock Input Specifications for CMOS
Value
Parameter
Symbol
Unit
Minimum
45
Maximum
1
Clock rise and fall time
t
RISE tFALL
ns
%
Clock duty cycle
55
Clock input jitter
tJIT
100
800
800
ps
Peak-to-peak at HT_REFCLK inputs
Peak-to-peak at PCIE_REFCLK inputs
500
500
mV
mV
Figure 3-5. Typical External Termination for CMOS Oscillator
REFCLK is floating.
3.3 V
10 nF
5 K
REFCLKP
500 - 800 mV
AVDD2/2
0V
1.6 - 2.5 kΩ
The common-mode level of AVDD2/2 is set internally by
the PLL receiver circuits.
Electrical and Thermal Characteristics
Page 28 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
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