Datasheet
CPC945 Bridge and Memory Controller
Preliminary
3.9 DDR2 SDRAM Interface Specifications
The double data rate, 128/144-bit-wide SDRAM interface operates in synchronous mode at up to 266 MHz
(533 million transfers per second). Registers in the CPC945 are used to meet the timing requirements of the
DDR2 dual inline memory module (DIMM) standard. The settings are determined experimentally and must
match the timing requirements of the memory DIMMs and the card design. Care must be taken to match the
data (DQ) latency between bits within a byte lane. The timing between byte lanes is adjustable by the internal
registers.
Note: A thorough and comprehensive tuning process must be followed during board bring-up with several
different parts. Tuning should be done with all possible memory configurations planned for the application.
For further information about the tuning process, review the Memory Signal Delay Tuning application note.
Additionally, parts used for this initial tuning phase should cover the entire manufacturing process window.
Contact your IBM sales or marketing representative for information about obtaining samples of parts outside
of the production part number PSRO range.
Note: Achieving a maximum memory transfer rate of 533 MTps and driving eight ranks of memory simulta-
neously is not possible without the use of external components to redrive the load.
3.10 HyperTransport Interface Specifications
The HyperTransport interface is a source-synchronous interface that latches data at a clock edge. Because
the interface can support up to 1600 MTps, careful consideration is necessary to ensure that the clock and
signal alignments and flight times are matched in a board design. The CPC945 meets the module require-
ments and specifications of the HyperTransport 1.04 Specification, which should be used to design this inter-
face.
Electrical and Thermal Characteristics
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A15-6009-03
December 18, 2007 - IBM Confidential
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