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IBM25CPC945CQ3C-2 参数 Datasheet PDF下载

IBM25CPC945CQ3C-2图片预览
型号: IBM25CPC945CQ3C-2
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC, CMOS, PBGA1182,]
分类和应用:
文件页数/大小: 69 页 / 1861 K
品牌: IBM [ IBM ]
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Datasheet  
Preliminary  
CPC945 Bridge and Memory Controller  
3.4 Recommended dc Operating Conditions  
Device operation beyond the conditions specified in Table 3-4 is not recommended. Extended operation  
beyond the recommended conditions can affect device reliability.  
Table 3-4. Recommended Functional dc Operating Ratings (Page 1 of 2)  
Parameter  
Symbol  
VDD  
Minimum  
1.45  
Typical  
1.50  
1.8  
Maximum  
1.55  
1.9  
Units  
Notes  
1.5 V core logic supply voltage  
V
V
V
V
1.8 V DDR interface supply voltage  
1.3 V - 1.5 V processor interface supply voltage  
2.5 V I2C, miscellaneous I/O supply voltage  
VDD3  
VDD2  
VDD5  
1.7  
1.35  
1.45  
2.5  
1.6  
4
2.3  
2.7  
1.2 V HyperTransport data interface supply  
voltage  
VDD4  
AVDDx  
AVDD  
1.14  
1.6  
1.2  
1.8 - 2.5  
1.5  
1.26  
2.8  
V
V
V
HyoerTransport and PCIe phase-locked loop  
(PLL) supply voltage - AVDD2, AVDDA,  
AVDDB  
DDR and processor interface PLL supply  
voltage - AVDD  
1.4  
1.6  
1
V
V
V
DD active current  
DD2 active current  
DD3 active current  
IDD  
IDD2  
IDD3  
IDD4  
IDD5  
IPLL  
1.7  
10.0  
1.0  
2.7  
A
A
2
2
2.8  
A
2
VDD4 active current  
0.17  
0.08  
0.1  
A
2
V
V
DD5 active current  
A
2
PLL active current - AVDD  
A
2, 3  
2
VDD active power  
PDD  
PDD2  
PDD3  
PDD4  
PDD5  
14.25  
1.4  
W
W
W
W
W
W
W
W
V
V
V
DD2 active power  
DD3 active power  
2
5.0  
2
VDD4 active power  
DD5 active power  
0.25  
0.2  
2
V
2
AVDD2, AVDDA, AVDDB active power  
VPLL active power  
0.1  
PAVDDx  
PPLL  
0.1  
2, 3  
2
Total device power  
2.5 V input logic high  
Notes:  
PT  
21.5  
VIH2  
1. The PLL analog power supply and ground pins must be filtered with a inductive-capacitive (LC) filter. See Figure 3-1, Analog VDD  
Filtering for the HyperTransport and PCI Express Phase-Locked Loops, on page 24 for details.  
2. At 533 MHz core frequency, 533 MTps DDR2, 1250 MTps processor interface, nominal supply voltages, and 70°C junction temper-  
ature. Configurations with lower speeds and narrower interfaces (333 MTps 64-bit DDR2, 600 MTps processor interface, 400  
MTps 8-bit HyperTransport) will consume less power. Contact IBM applications engineering for more details.  
3. The four PLLs consume current from both the VDD and VPLL AVDD, AVDD2, AVDDA, AVDDB supplies. These currents are small  
relative to the total core current.  
4. Processor interface supply voltage VDD2 can vary from 1.3 V to 1.5 V, depending on system or card design requirements and pro-  
cessor I/O voltage specifications. Perform necessary simulations or provide a variable voltage and determine, experimentally,  
which voltage best meets their requirements. This voltage must be the same for both processor (OVDD) and bridge (VDD2).  
5. The core voltage must be brought up first, followed by the I/O voltages. Note that correct I2C slave interface operation depends on  
stable core, processor I/O, and DDR I/O voltages. No voltage should be applied to an I/O pad if the associated power supply is not  
turned on.  
A15-6009-03  
December 18, 2007 - IBM Confidential  
Electrical and Thermal Characteristics  
Page 23 of 69  
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